The present invention relates generally to semiconductor fabrication and more specifically to, a test macro for use with a multi-patterning lithography process.
High level macros are designed to provide connections to various lower level electrical devices, such as transistors. As the scale and type of these lower level devices continues to evolve, the design of these high level macros has become more complex. In addition, various techniques for are used for manufacturing integrated circuits embodying the macros.
For integrated circuits having lower level devices, which are referred to as high pitch devices, a multiple patterning lithography processes are often utilized for manufacturing the integrated circuit. A multi-patterning lithography process includes subsequent patterning of metal layers on an integrated circuit. Multiple patterning is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. A simple example of multiple patterning is double patterning, where a conventional lithography process is enhanced to produce double the expected number of features. In general, the resolution of a photoresist pattern begins to blur at around 45 nm half-pitch. Accordingly, double patterning was introduced for the 32 nm half-pitch node and below.
Currently, integrated circuits formed by a multiple patterning lithography process experience can failures due to overlay shift. As used herein, an overlay shift is the unintended overlay of metal layers that are not designed to be connected during the manufacturing process. In many cases, it is difficult to determine which step of the multiple lithography processes is the cause of the overlay shift.